FIELD OF THE INVENTION
This invention relates to an improved semiconductor structure for high-density, dynamic random access memory (DRAM) arrays, and more particularly, to a structure that can be implemented with a small feature size and is efficient in area utilization.
This application is related to U.S. patent application Ser. No. 07/900,038, filed Jun. 17, 1992, entitled "Vertical Gate Transistor With Low Temperature Epitaxial Channel" and assigned to the assignee of this application, which application issued on Feb. 1, 1994 as U.S. Pat. No. 5,284,456.
Because the conventional planar capacitor cell cannot achieve sufficient storage capacitance, various three-dimensional cell structures have been proposed in the prior art for producing mega-bit DRAMs. Cells using trench capacitors have been proposed in order to maintain sufficient storage capacitance. An article entitled "A New Soft-Error Immune DRAM Cell With a Transistor On a Lateral Epitaxial Silicon Layer (Tole Cell)", by T. Kubota et al., IEEE Journal, 1987, pgs. 344-347, discloses a DRAM cell with trench capacitors. This cell is produced by a silicon-on-insulator fabrication technology that combines epitaxial lateral overgrowth and preferential polishing to produce a cell with a conventional gate structure for each cell.
FIG. 1A is a schematic diagram of a conventional four-by-four array of dynamic random access (DRAM) cells.
This conventional array can be rearranged to the shared-gate, double-bit array shown in FIG. 1B. This latter array layout can be implemented with a vertical gate FET described in the aforementioned co-pending application. It also allows both bit and substrate contacts to be shared by adjacent cells. In an effort to reduce the cost per memory cell, the state of the art in DRAM technology continuously seeks to increase the cell density per integrated circuit chip. This requires small feature size, preferably using conventional photolithography process steps, and efficient use of the semiconductor chip area.